(a) Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a trench in a semiconductor device and a formation method thereof.
(b) Description of the Related Art
A LOCOS (local oxidation of silicon) isolation structure, in which a semiconductor substrate is thermally oxidized using a nitride layer as a mask, is widely used as an isolation structure for conventional semiconductor devices. However, the formation of a bird's beak configuration and an increase in a field region result from LOCOS isolation. As a result, there are limitations to how small the device can be made when using the LOCOS isolation structure.
In an effort to overcome these problems, STI (shallow trench isolation) is used in place of LOCOS isolation. In STI, a trench is formed in a semiconductor substrate, and an insulation material is filled in the trench. Since the formation is limited to the size of the trench, which has as its object size a field region size, this configuration works favorably toward making the semiconductor device small.
U.S. Pat. Nos. 5,521,422, 5,956,598, 5,989,977, 6,001,706, and 6,495,430 are conventional techniques related to STI.
A conventional method for forming a trench in a semiconductor device will be described with reference to FIGS. 1a and 1b. 
With reference first to FIG. 1a, a pad oxide layer 2 then a silicon nitride layer 3 are deposited on a semiconductor substrate 1. Next, a photoresist layer is deposited on the silicon nitride layer 3, then the photoresist layer is exposed to remove a portion thereof corresponding to where a trench is to be formed to thereby realize a photoresist layer pattern 4.
Subsequently, with reference to FIG. 1b, using the photoresist layer pattern 4 as a mask, the exposed portion of the silicon nitride layer 3 then the pad oxide layer 2 and a predetermined section of the semiconductor substrate 1 (i.e., a section corresponding to a predetermined depth) under the removed section of the pad oxide layer 2 are dry-etched. A trench 100 is therefore formed in the semiconductor substrate 1. The photoresist layer pattern 4 is removed after the formation of the trench 100, then a cleaning process is performed.
Next, a liner oxide layer 5 is formed over all exposed elements of the silicon nitride layer 3, the pad oxide layer 2, and inner walls of the trench 100, after which a trench oxide layer 6 is thickly deposited on the liner oxide layer 5 at least until the trench 100 is completely filled.
The liner oxide layer 5 minimizes the stress transferred to the trench region during deposition of the trench oxide layer 6. The liner oxide layer 5 also prevents the uneven formation of the trench oxide layer 6 caused by differences in deposition rates on the semiconductor substrate 1 and the silicon nitride layer 3, which results from the difference in the materials of the semiconductor substrate 1 and the silicon nitride layer 3. In addition, with the formation of the liner oxide layer 5, upper corner areas of the semiconductor substrate 1 adjacent to the trench 100 are rounded (i.e., prevented from being sharply pointed) following a subsequent trench isolation process.
Next, chemical-mechanical polishing is performed on the trench oxide layer 6 and the liner oxide layer 5 until the silicon nitride layer 3 is exposed, that is, until the trench oxide layer 6 and the liner oxide layer 5 are flattened and flush with the silicon nitride layer 3. This completes the trench isolation process.
However, in the conventional STI as described above, it is difficult to realize the rounding of the upper corners of the semiconductor substrate that are adjacent to the trench through only the formation of the liner oxide layer. This becomes increasingly difficult as the degree of integration of the device is raised.
Accordingly, upper areas of the semiconductor substrate adjacent to the trench are formed with sharp corners. If an electric charge is concentrated in these corner areas, a dielectric breakdown voltage is reduced. There is therefore a need to realize a method for rounding the upper corner areas of the semiconductor substrate adjacent to the trench.